PIC12F629-I View Datasheet(PDF) - Microchip Technology
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PIC12F629-I Datasheet PDF : 132 Pages
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PIC12F629/675
3.2.2 INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of GPIO. This will end the
mismatch condition.
b) Clear the flag bit GPIF.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
REGISTER 3-4:
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
U-0
—
bit 7
U-0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—
IOC5
IOC4
IOC3
IOC2
IOC1
R/W-0
IOC0
bit 0
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
recognized.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
DS41190C-page 21
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