PIC12F629-I View Datasheet(PDF) - Microchip Technology
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PIC12F629-I Datasheet PDF : 132 Pages
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3.3.3 GP2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from the comparator
FIGURE 3-2:
Data Bus
DQ
WR
WPU
CK Q
BLOCK DIAGRAM OF GP2
Analog
Input Mode
VDD
Weak
RD
WPU
WR
PORT
DQ
CK Q
WR
TRISIO
DQ
CK Q
RD
TRISIO
GPPU
COUT
Enable
Analog
Input
Mode
VDD
COUT 1
0
I/O pin
VSS
Analog
Input Mode
RD
PORT
WR
IOC
DQ
CK Q
RD
IOC
Interrupt-on-Change
QD
EN
QD
EN
RD PORT
To TMR0
To INT
To A/D Converter
PIC12F629/675
3.3.4
GP3/MCLR/VPP
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3:
BLOCK DIAGRAM OF GP3
Data Bus
RESET
RD
VSS
TRISIO
RD
PORT
DQ
WR
IOC
CK Q
RD
IOC
Interrupt-on-Change
MCLRE
I/O pin
MCLRE
VSS
QD
EN
QD
EN
RD PORT
2003 Microchip Technology Inc.
DS41190C-page 23
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