PIC12F609/615/617/12HV609/615
5.2.4.6 GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN
Figure 5-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
• PWM output, alternate pin(1, 2)
• a crystal/resonator connection
• a clock input
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
FIGURE 5-5:
BLOCK DIAGRAM OF GP5
Data Bus
DQ
WR
WPU
CK Q
RD
WPU
WR
GPIO
DQ
CK Q
WR
TRISIO
DQ
CK Q
RD
TRISIO
RD
GPIO
WR
IOC
DQ
CK Q
RD
IOC
Interrupt-on-
Change
Q S(2)
R
Write ‘0’ to GBIF
From other
GP<4:0> pins
To Timer1
Note 1: Timer1 LP Oscillator enabled.
2: Set has priority over Reset.
INTOSC
Mode
TMR1LPEN(1)
VDD
Weak
GPPU
Oscillator
Circuit
OSC2
VDD
INTOSC
Mode
I/O Pin
VSS
QD
EN
Q1
QD
EN
RD GPIO
2010 Microchip Technology Inc.
DS41302D-page 51