PIC12F609/615/617/12HV609/615
9.0 COMPARATOR MODULE
The comparator can be used to interface analog
circuits to a digital circuit by comparing two analog
voltages and providing a digital indication of their
relative magnitudes. The comparator is a very useful
mixed signal building block because it provides analog
functionality independent of the program execution.
The Analog Comparator module includes the following
features:
• Programmable input section
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep
• PWM shutdown
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input
• Programmable voltage reference
• User-enable Comparator Hysteresis
than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
FIGURE 9-1:SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VIN-
VIN+
Output
9.1 Comparator Overview
The comparator is shown in Figure 9-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at VIN+ is less
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
FIGURE 9-2:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
CMCH
GP1/CIN0-
GP4/CIN1-
0
MUX
1
CMON(1)
CMVIN-
CMVIN+
CMPOL
DQ
Q1 EN
DQ
Q3*RD_CMCON0 EN
CL
Reset
To
Data Bus
RD_CMCON0
Set CMIF
To PWM Auto-Shutdown
CMSYNC
CMOE
CMR
GP0/CIN+
FixedRef
CVREF
0
MUX
CMVREF
1
0
MUX
1
CMPOL
From Timer1
Clock
DQ
0
MUX
1
COUT(4)
SYNCCMOUT
To Timer1 Gate
CMVREN
Note 1:
2:
3:
4:
When CMON = 0, the comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (FOSC).
Q1 is held high during Sleep mode.
Output shown for reference only. See I/O port pin diagram for more details.
2010 Microchip Technology Inc.
DS41302D-page 67