PIC16C432-I View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C432-I

OTP 8-Bit CMOS MCU with LIN Transceiver

Microchip Technology 

PIC16C432

6.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple-counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns), divided by the prescaler value. The only

requirement on T0CKI high and low time is that they do

not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical specification of the desired device.

6.2.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the TMR0 is

actually incremented. Figure 6-5 shows the delay from

the external clock edge to the timer incrementing.

FIGURE 6-5:

TIMER0 TIMING WITH EXTERNAL CLOCK

External Clock Input or

Prescaler Output(2)

External Clock/Prescaler

Output after Sampling

Increment Timer0 (Q4)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

(1)

(3)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (Duration of Q = TOSC). There-

fore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

 2000-2013 Microchip Technology Inc.

Preliminary

DS41140C-page 29

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