PIC16C432-I View Datasheet(PDF) - Microchip Technology
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PIC16C432-I Datasheet PDF : 106 Pages
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PIC16C432
9.4.5 TIMEOUT SEQUENCE
On power-up, the timeout sequence is as follows: First
PWRT timeout is invoked after POR has expired, then
OST is activated. The total timeout will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no timeout at all. Figure 9-8,
Figure 9-8 and Figure 9-9 depict timeout sequences.
Since the timeouts occur from the POR pulse, if MCLR
is kept low long enough, the timeouts will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC® device operating in
parallel.
Table 9-5 shows the RESET conditions for some spe-
cial registers, while Table 9-6 shows the RESET condi-
tions for all the registers.
9.4.6
POWER CONTROL (PCON)/STATUS
REGISTER
The power control/status register, PCON (address
8Eh), has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOR = 0, indicating
that a brown-out has occurred. The BOR status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent RESET, if POR is ‘0’, it will indicate that a Power-
on Reset must have occurred (VDD may have gone too
low).
TABLE 9-3: TIMEOUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
Brown-out Reset
72 ms + 1024 TOSC
72 ms
Wake-up
from SLEEP
1024 TOSC
—
TABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
X
1
1
Power-on Reset
0
X
0
X
Illegal, TO is set on POR
0
X
X
0
Illegal, PD is set on POR
1
0
X
X
Brown-out Reset
1
1
0
u
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP
Legend: x = unknown, u = unchanged
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 49
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