PIC16LC62T-10E/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC62T-10E/SP

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

12.2.2 USART ASYNCHRONOUS RECEIVER

The receiver block diagram is shown in Figure 12-10.

The data comes in the RC7/RX/DT pin and drives the

data recovery block. The data recovery block is actually

a high speed shifter operating at x16 times the baud

rate, whereas the main receive serial shifter operates

at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the receive (serial) shift reg-

ister (RSR). After sampling the STOP bit, the received

data in the RSR is transferred to the RCREG register (if

it is empty). If the transfer is complete, flag bit RCIF

(PIR1<5>) is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read only bit which is

cleared by the hardware. It is cleared when the RCREG

register has been read and is empty. The RCREG is

double buffered register, i.e., it is a two deep FIFO. It is

FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM

possible for two bytes of data to be received and trans-

ferred to the RCREG FIFO and a third byte begin shift-

ing to the RSR register. On the detection of the STOP

bit of the third byte, if the RCREG is still full, then the

overrun error bit, OERR (RCSTA<1>) will be set. The

word in the RSR register will be lost. The RCREG reg-

ister can be read twice to retrieve the two bytes in the

FIFO. Overrun bit OERR has to be cleared in software.

This is done by resetting the receive logic (CREN is

cleared and then set). If bit OERR is set, transfers from

the RSR register to the RCREG register are inhibited,

so it is essential to clear overrun bit OERR if it is set.

Framing error bit FERR (RCSTA<2>) is set if a stop bit

is detected as clear. Error bit FERR and the 9th receive

bit are buffered the same way as the receive data.

Reading the RCREG register will load bits RX9D and

FERR with new values. Therefore it is essential for the

user to read the RCSTA register before reading

RCREG in order not to lose the old FERR and RX9D

information.

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

CREN

÷ 64

or

÷ 16

OERR

FERR

MSb

RSR register

Stop (8) 7 • • • 1

LSb

0 Start

RC7/RX/DT

Pin Buffer

and Control

Data

Recovery

RX9

SPEN

RX9D

RCREG register

FIFO

Interrupt

RCIF

RCIE

8

Data Bus

FIGURE 12-11: ASYNCHRONOUS RECEPTION

RC7/RX/DT (pin)

Rcv shift

reg

Rcv buffer reg

Read Rcv

buffer reg

RCREG

Start

bit bit0 bit1

Start

bit7/8 Stop bit bit0

bit

WORD 1

RCREG

RCIF

(interrupt flag)

Start

bit7/8 Stop bit

bit

WORD 2

RCREG

bit7/8 Stop

bit

OERR bit

CREN bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing overrun error bit OERR to be set.

DS30234D-page 114

© 1997 Microchip Technology Inc.

Share Link: