PIC16C77X
FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
A/D CLK
131
130
1/2 Tcy
A/D DATA
9
8
7
6
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF
GO
SAMPLE
132
SAMPLING STOPPED
DONE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 15-10 A/D CONVERSION REQUIREMENTS
Parameter
No.
130*
Sym Characteristic
TAD A/D clock period
130*
TAD A/D Internal RC
oscillator period
131*
132*
TCNV
Conversion time (not
including
acquisition time)
(Note 1)
TACQ Acquisition Time
Min
1.6
3.0
3.0
2.0
—
Note 2
Typ†
—
—
6.0
4.0
13TAD
11.5
Max Units
Conditions
—
s Tosc based, VREF 2.5V
—
s Tosc based, VREF full range
ADCS1:ADCS0 = 11 (RC mode)
9.0
s
At VDD = 2.5V
6.0
s
At VDD = 5.0V
—
TAD Set GO bit to new data in A/D result
register
—
s
5*
—
—
s The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1LSb (i.e
1mV @ 4.096V) from the last sam-
pled voltage (as stated on CHOLD).
134*
TGO Q4 to A/D clock start
—
TOSC/2
—
— If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.6 for minimum conditions.
DS30275B-page 166
Advance Information
1999-2013 Microchip Technology Inc.