PIC16LC773-I/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC773-I/SS Datasheet PDF : 202 Pages
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PIC16C77X
8.1.5 SLAVE MODE
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
While in slave mode the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in sleep mode, the slave can transmit/receive
data. When a byte is received the device will wake-up
from sleep.
8.1.6 SLAVE SELECT SYNCHRONIZATION
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode with SS pin control
enabled (SSPCON<3:0> = 0100). The pin must not
be driven low for the SS pin to function as an input.
TRISA<5> must be set. When the SS pin is low,
transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output.
External pull-up/ pull-down resistors may be desirable,
depending on the application.
Note:
When the SPI module is in Slave Mode
with SS pin control enabled, (SSP-
CON<3:0> = 0100) the SPI module will
reset if the SS pin is set to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then SS pin control must be
enabled.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 8-7: SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
bit7
bit6
bit7
bit7
bit0
bit0
bit7
Next Q4 cycle
after Q2
DS30275B-page 60
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