PIC16C77X
8.2.3 SLEEP OPERATION
8.2.4 EFFECTS OF A RESET
While in sleep mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep (if the SSP interrupt is enabled).
A reset diables the SSP module and terminates the
current transfer.
TABLE 8-3 REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
10Bh,18Bh
0Ch
8Ch
INTCON
PIR1
PIE1
GIE
PSPIF(1)
PSPIE(1)
PEIE
ADIF
ADIE
T0IE INTE RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
0Dh
PIR2
LVDIF
—
—
— BCLIF
—
—
CCP2IF 0--- 0--0 0--- 0--0
8Dh
PIE2
LVDIE
—
—
— BCLIE
—
—
CCP2IE 0--- 0--0 0--- 0--0
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h
SSPCON2
GCEN AKSTAT AKDT AKEN RCEN
PEN
RSEN
SEN 0000 0000 0000 0000
94h
Legend:
Note 1:
2:
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
These bits are reserved on the 28-pin devices, always maintain these bits clear.
These bits are reserved on these devices, always maintain these bits clear.
0000 0000
DS30275B-page 70
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