PIC16LC8X-04 View Datasheet(PDF) - Microchip Technology
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PIC16LC8X-04 Datasheet PDF : 117 Pages
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7.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
• EECON1
• EECON2
• EEDATA
• EEADR
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC16C8X devices have 64 bytes of
data EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and
write. A byte write automatically erases the location
and writes the new data (erase before write). The
EEPROM data memory is rated for high erase/write
cycles. The write time is controlled by an on-chip timer.
The write-time will vary with voltage and temperature
as well as from chip to chip. Please refer to AC
specifications for exact limits.
PIC16C8X
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
7.1 EEADR
The EEADR register can address up to a maximum of
256 bytes of data EEPROM. Only the first 64 bytes of
data EEPROM are implemented and only six of the
eight bits in the register (EEADR<5:0>) are required.
The upper two bits are address decoded. This means
that these two bits should always be '0' to ensure that
the address is in the 64 byte memory space.
FIGURE 7-1: EECON1 REGISTER (ADDRESS 88h)
U
—
bit7
bit 7:5
bit 4
bit 3
bit 2
bit 1
bit 0
U
U
R/W-0 R/W-x R/W-0
—
—
EEIF WRERR WREN
Unimplemented: Read as '0'
R/S-0
WR
R/S-x
RD
bit0
R = Readable bit
W = Writable bit
S = Settable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only be
set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only be
set (not cleared) in software).
0 = Does not initiate an EEPROM read
© 1995 Microchip Technology Inc.
Thi d
t
t d ith F M k 4 0 4
DS30081F-page 33
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