PIC16LC8X View Datasheet(PDF) - Microchip Technology
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PIC16LC8X Datasheet PDF : 117 Pages
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8.5.1 INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 8.8) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
8.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 6.0).
8.5.3 PORT RB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 5.2).
Note 1: For the PIC16C84 Only;
If a change on an I/O pin should occur
when a read operation of PORTB is being
executed (start of the Q2 cycle), the RBIF
interrupt flag bit may not get set.
Note 2: For all other PIC16C8X devices;
For a change on the I/O pin to be
recognized, the pulse width must be at
least TCY wide.
PIC16C8X
8.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and
STATUS register). This is implemented in software.
Example 8-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 8-1 does the following:
a) Stores the W register.
b) Stores the STATUS register in STATUS_TEMP.
c) Executes the Interrupt Service Routine code.
d) Restores the STATUS (and bank select bit)
register.
e) Restores the W register.
EXAMPLE 8-1:
PUSH
ISR
POP
MOVWF
SWAPF
MOVWF
:
:
:
:
SWAPF
MOVWF
SWAPF
SWAPF
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP
STATUS, W
STATUS_TEMP
STATUS_TEMP, W
STATUS
W_TEMP, F
W_TEMP, W
; Copy W to TEMP register,
; Swap status to be saved into W
; Save status to STATUS_TEMP register
:
; Interrupt Service Routine
; should configure Bank as required
;
; Swap nibbles in STATUS_TEMP register
; and place result into W
; Move W into STATUS register
; (sets bank to original state)
; Swap nibbles in W_TEMP and place result in W_TEMP
; Swap nibbles in W_TEMP and place result into W
© 1995 Microchip Technology Inc.
DS30081F-page 49
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