PIC16CE624T-04SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16CE624T-04SS Datasheet PDF : 113 Pages
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PIC16CE62X
FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL (A) (B)
(C)
(D)
SDA
(C) (A)
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
FIGURE 6-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
6.2 Device Addressing
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don’t care bits.
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected. (Figure 6-3). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
FIGURE 6-3: CONTROL BYTE FORMAT
Read/Write Bit
Device Select
Bits
Don’t Care
Bits
S 1 0 1 0 X X X R/W ACK
Start Bit
EEPROM Address
Acknowledge Bit
© 1999 Microchip Technology Inc.
DS40182C-page 31
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