PIC16CE62X
13.6 EEPROM Timing
FIGURE 13-10: BUS TIMING DATA
TF
TLOW
THIGH
SCL
TSU:STA
SDA
IN
TSP
THD:STA
THD:DAT
SDA
OUT
TAA
THD:STA
TAA
TR
TSU:DAT
TSU:STO
TBUF
TABLE 13-7: AC CHARACTERISTICS
Parameter
Symbol
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE Units
Remarks
Min. Max. Min. Max.
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
THIGH 4000
—
600
—
ns
Clock low time
TLOW 4700
—
1300
—
ns
SDA and SCL rise time
TR
— 1000 —
300 ns (Note 1)
SDA and SCL fall time
TF
—
300
—
300 ns (Note 1)
START condition hold time
THD:STA 4000
—
600
—
ns After this period the first
clock pulse is generated
START condition setup time TSU:STA 4700 —
600
—
ns Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
0
—
ns (Note 2)
Data input setup time
TSU:DAT 250
—
100
—
ns
STOP condition setup time
TSU:STO 4000
—
600
—
ns
Output valid from clock
TAA
— 3500 —
900 ns (Note 2)
Bus free time
TBUF
4700
—
1300
—
ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
—
250 20 + 0.1 250
ns (Note 1), CB ≤ 100 pF
CB
Input filter spike suppression
TSP
(SDA and SCL pins)
—
50
—
50
ns (Note 3)
Write cycle time
TWR
—
10
—
10
ms Byte or Page mode
Endurance
—
10M
1M
—
10M
1M
—
cycles
25°C, VCC = 5.0V, Block
Mode (Note 4)
Note 1:
2:
3:
4:
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns)
of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike sup-
pression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website.
© 1999 Microchip Technology Inc.
DS40182C-page 95