DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PIC12F1822T-I/SL View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
PIC12F1822T-I/SL Datasheet PDF : 398 Pages
First Prev 351 352 353 354 355 356 357 358 359 360 Next Last
PIC12F/LF1822/16F/LF1823
TABLE 29-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
30 TMCL MCLR Pulse Width (low)
2
— — s VDD = 3.3-5V, -40°C to +85°C
5
— — s VDD = 3.3-5V
31 TWDTLP Low-Power Watchdog Timer
10 18 27 ms VDD = 3.3V-5V
Time-out Period (No Prescaler)
32
TOST Oscillator Start-up Timer Period(1), (2) — 1024 — Tosc (Note 3)
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ
I/O high-impedance from MCLR Low —
or Watchdog Timer Reset
— 2.0 s
35 VBOR Brown-out Reset Voltage
2.38 2.5 2.65
1.80 1.9 2.05
V BORV=2.5V
BORV=1.9V
36* VHYST Brown-out Reset Hysteresis
0 25 50 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response
Time
1
3
5
s VDD VBOR
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 29-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
TMR0 or
TMR1
45
46
47
49
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 353

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]