PIC16F688T-I/ST View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F688T-I/ST

14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC16F688

10.4.2.3 EUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 10.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

10.4.2.4 Synchronous Slave Reception Set-

up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

RCIE bit.

3. If 9-bit reception is desired, set the RX9 bit.

4. Set the CREN bit to enable reception.

5. The RCIF bit will be set when reception is

complete. An interrupt will be generated if the

RCIE bit was set.

6. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

register.

7. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

8. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

register or by clearing the SPEN bit which resets

the EUSART.

TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

BAUDCTL ABDOVF RCIDL

—

SCKP BRG16

—

WUE ABDEN 01-0 0-00 01-0 0-00

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF 0000 000x 0000 000x

PIE1

EEIE

ADIE

RCIE

C2IE

C1IE

OSFIE

TXIE TMR1IE 0000 0000 0000 0000

PIR1

EEIF

ADIF

RCIF

C2IF

C1IF

OSFIF

TXIF TMR1IF 0000 0000 0000 0000

RCREG EUSART Receive Data Register

0000 0000 0000 0000

RCSTA

SPEN

RX9

SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG

BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISC

—

—

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

TXREG EUSART Transmit Data Register

0000 0000 0000 0000

TXSTA

CSRC

TX9

TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

DS41203D-page 108

© 2007 Microchip Technology Inc.

Share Link: