PIC16F688
FIGURE 14-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
33
32
I/O pins
Note 1: Asserted low.
30
31
34
34
FIGURE 14-7:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR
VBOR + VHYST
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33*
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
DS41203D-page 156
© 2007 Microchip Technology Inc.