PIC16F688
FIGURE 7-8:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VDD
VREN
CVREF to
Comparator
Input
8R
R
R
16-1 Analog
MUX
15
14
2
1
0
VR<3:0>(1)
R
R
8R
VRR
VREN
VR<3:0> = 0000
VRR
Note 1:
Care should be taken to ensure VREF remains
within the comparator common mode input
range. See Section 14.0 “Electrical Specifica-
tions” for more detail.
TABLE 7-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ANSEL
CMCON0
CMCON1
INTCON
PIE1
PIR1
PORTA
PORTC
TRISA
TRISC
VRCON
Legend:
ANS7
ANS6 ANS5 ANS4 ANS3 ANS2 ANS1
ANS0 1111 1111 1111 1111
C2OUT C1OUT C2INV C1INV CIS
CM2
CM1
CM0
0000 0000 0000 0000
—
—
—
—
—
— T1GSS C2SYNC ---- --10 ---- --10
GIE
PEIE
T0IE INTE RAIE T0IF INTF
RAIF
0000 000x 0000 000x
EEIE
ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000
EEIF
ADIF
RCIF C2IF C1IF OSFIF TXIF
TMR1IF 0000 0000 0000 0000
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--x0 x000 --x0 x000
—
—
RC5
RC4
RC3 RC2
RC1
RC0
--xx 0000 --xx 0000
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
—
—
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
VREN
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
DS41203D-page 64
© 2007 Microchip Technology Inc.