PIC16F688
TABLE 8-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC Clock Source
ADCS<2:0>
20 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
100 ns(2)
250 ns(2)
500 ns(2)
2.0 μs
100
200 ns(2)
500 ns(2)
1.0 μs(2)
4.0 μs
001
400 ns(2)
1.0 μs(2)
2.0 μs
8.0 μs(3)
101
800 ns(2)
2.0 μs
4.0 μs
16.0 μs(3)
010
1.6 μs
4.0 μs
8.0 μs(3)
32.0 μs(3)
110
3.2 μs
8.0 μs(3)
16.0 μs(3)
64.0 μs(3)
x11
2-6 μs(1,4)
2-6 μs(1,4)
2-6 μs(1,4)
2-6 μs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 8-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
© 2007 Microchip Technology Inc.
DS41203D-page 67