PIC16F688
8.2.6 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 8-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
ADFM
VCFG
—
CHS2
CHS1
bit 7
R/W-0
CHS0
R/W-0
GO/DONE
R/W-0
ADON
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4-2
bit 1
bit 0
ADFM: A/D Conversion Result Format Select bit
1 = Right justified
0 = Left justified
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
Unimplemented: Read as ‘0’
CHS<2:0>: Analog Channel Select bits
000 = AN0
001 = AN1
010 = AN2
011 = AN3
100 = AN4
101 = AN5
110 = AN6
111 = AN7
GO/DONE: A/D Conversion Status bit
1 = A/D Conversion cycle in progress. Setting this bit starts an A/D Conversion cycle.
This bit is automatically cleared by hardware when the A/D Conversion has completed.
0 = A/D Conversion completed/not in progress
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
REGISTER 8-2: ADCON1: A/D CONTROL REGISTER 1
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
—
ADCS2
ADCS1
ADCS0
—
—
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
Unimplemented: Read as ‘0’
© 2007 Microchip Technology Inc.
DS41203D-page 71