PIC16C712T-04/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C712T-04/SO

8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM

Microchip Technology 

PIC16C712/716

7.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTB data latch,

the TRISCCP<2> bit must be cleared to make the

CCP1 pin an output.

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is neither the PORTB I/O

data latch nor the DATACCP latch.

Figure 7-5 shows a simplified block diagram of the CCP

module in PWM mode.

For a step by step procedure on how to set up the CCP

module for PWM operation, see Section 7.3.3.

FIGURE 7-5: SIMPLIFIED PWM BLOCK

DIAGRAM

Duty cycle registers

CCPR1L

CCP1CON<5:4>

CCPR1H (Slave)

Comparator

R

TMR2

(Note 1)

S

Comparator

PR2

Clear Timer,

CCP1 pin and

latch D.C.

Q

RB3/CCP1

TRISCCP<2>

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

A PWM output (Figure 7-6) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 7-6: PWM OUTPUT

Period = PR2+1

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle (CCPR1H)

TMR2 = PR2

7.3.1 PWM PERIOD

The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the fol-

lowing formula:

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note:

The Timer2 postscaler (see Section 6.0) is

not used in the determination of the PWM

frequency. The postscaler could be used to

have a servo update rate at a different fre-

quency than the PWM output.

7.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM

frequency:

( ) = log

FOSC

FPWM

bits

log(2)

Note:

If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be

cleared.

For an example PWM period and duty cycle calcula-

tion, see the PICmicro™ Mid-Range Reference

Manual, (DS33023).

DS41106A-page 42

Preliminary

© 1999 Microchip Technology Inc.

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