PIC16C712T-04/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16C712T-04/SO

8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM

Microchip Technology 

PIC16C712/716

8.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD). The

source impedance affects the offset voltage at the ana-

log input (due to pin leakage current). The maximum

recommended impedance for analog sources is 10

kΩ. After the analog input channel is selected

(changed) this acquisition must be done before the

conversion can be started.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range Reference Manual,

(DS33023). This equation calculates the acquisition

time to within 1/2 LSb error (512 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified accuracy.

Note:

When the conversion is started, the hold-

ing capacitor is disconnected from the

input pin.

FIGURE 8-4: ANALOG INPUT MODEL

Rs ANx

VA

CPIN

5 pF

VDD

VT = 0.6V

VT = 0.6V

RIC ≤ 1k

Sampling

Switch

SS RSS

I leakage

± 500 nA

CHOLD

= DAC capacitance

= 51.2 pF

VSS

Legend CPIN

= input capacitance

VT

= threshold voltage

I leakage = leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

6V

5V

VDD 4V

3V

2V

5 6 7 8 9 10 11

Sampling Switch

(kΩ)

DS41106A-page 48

Preliminary

© 1999 Microchip Technology Inc.

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