PIC16C712/716
FIGURE 12-3: CLKOUT AND I/O TIMING
Q4
Q1
OSC1
10
Q2
Q3
11
CLKOUT
13
14
I/O Pin
(input)
17
I/O Pin
(output)
old value
20, 21
Note: Refer to Figure 12-1 for load conditions.
19
18
15
12
16
new value
TABLE 12-3 CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min Typ† Max Units Conditions
10* TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns Note 1
11* TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns Note 1
12* TckR
CLKOUT rise time
—
35
100
ns
Note 1
13* TckF
CLKOUT fall time
—
35
100
ns Note 1
14* TckL2ioV CLKOUT ↓ to Port out valid
—
— 0.5TCY + 20 ns
Note 1
15* TioV2ckH Port in valid before CLKOUT ↑
Tosc + 200 —
—
ns
Note 1
16* TckH2ioI Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18* TosH2ioI OSC1↑ (Q2 cycle) to Port input Standard
18A*
invalid (I/O in hold time)
Extended (LC)
100
—
—
ns
200
—
—
ns
19* TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20* TioR
Port output rise time
Standard
—
10
40
ns
20A*
Extended (LC)
—
—
80
ns
21* TioF
Port output fall time
Standard
—
10
40
ns
21A*
Extended (LC)
—
—
80
ns
22††* TINP
INT pin high or low time
TCY
—
—
ns
23††* TRBP
RB7:RB4 change INT high or low time
TCY
—
—
ns
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS41106A-page 84
Preliminary
© 1999 Microchip Technology Inc.