PIC16C712/716
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
33
32
I/O Pins
Note: Refer to Figure 12-1 for load conditions.
30
34
31
34
FIGURE 12-5: BROWN-OUT RESET TIMING
VDD
BVDD
35
TABLE 12-4 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
—
—
µs VDD = 5V, -40°C to +125°C
31*
TWDT Watchdog Timer Time-out Period 7
(No Prescaler)
18
33 ms VDD = 5V, -40°C to +125°C
32
TOST Oscillation Start-up Timer Period — 1024 TOSC —
— TOSC = OSC1 period
33*
TPWRT Power-up Timer Period
28
72
132 ms VDD = 5V, -40°C to +125°C
34
TIOZ I/O Hi-impedance from MCLR
—
—
2.1 µs
Low or WDT reset
35
TBOR Brown-out Reset Pulse Width
100
—
—
µs VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
© 1999 Microchip Technology Inc.
Preliminary
DS41106A-page 85