PIC16C71X
Applicable Devices 710 71 711 715
FIGURE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
I/O Pins
33
32
30
31
34
34
Note: Refer to Figure 15-1 for load conditions.
TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
200
—
—
ns VDD = 5V, -40˚C to +85˚C
31
Twdt Watchdog Timer Time-out Period
7*
18
33* ms VDD = 5V, -40˚C to +85˚C
(No Prescaler)
32
Tost Oscillation Start-up Timer Period
— 1024 TOSC —
— TOSC = OSC1 period
33
Tpwrt Power-up Timer Period
28*
72
132* ms VDD = 5V, -40˚C to +85˚C
34
TIOZ I/O High Impedance from MCLR
—
—
100 ns
Low
*
These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
© 1997 Microchip Technology Inc.
DS30272A-page 143