PIC16C71X
Applicable Devices 710 71 711 715
TABLE 15-6: A/D CONVERTER CHARACTERISTICS
Param Sym Characteristic
No.
Min
Typ†
Max Units
Conditions
A01 NR Resolution
—
—
8 bits bits VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Absolute error
PIC16C71
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LC71
—
—
< ±2 LSb VREF = VDD = 3.0V (Note 3)
A03 EIL Integral linearity error
PIC16C71
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LC71
—
—
< ±2 LSb VREF = VDD = 3.0V (Note 3)
A04 EDL Differential linearity error PIC16C71
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LC71
—
—
< ±2 LSb VREF = VDD = 3.0V (Note 3)
A05 EFS Full scale error
PIC16C71
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LC71
—
—
< ±2 LSb VREF = VDD = 3.0V (Note 3)
A06 EOFF Offset error
PIC16C71
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LC71
—
—
< ±2 LSb VREF = VDD = 3.0V (Note 3)
A10 — Monotonicity
— guaranteed —
— VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage
3.0V
—
VDD + 0.3 V
A25 VAIN Analog input voltage
VSS - 0.3
—
VREF
V
A30 ZAIN Recommended impedance of analog
—
voltage source
—
10.0
kΩ
A40 IAD A/D conversion current (VDD)
—
180
—
µA Average current consump-
tion when A/D is on. (Note 1)
A50 IREF VREF input current (Note 2)
10
PIC16C71
—
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
To charge CHOLD see
Section 7.1.
—
40
µA During A/D Conversion cycle
—
—
PIC16LC71
—
—
1
mA During VAIN acquisition.
Based on differential of
VHOLD to VAIN.
To charge CHOLD see
Section 7.1.
10
µA During A/D Conversion cycle
*
†
Note 1:
2:
3:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VAIN must be between VSS and VREF.
© 1997 Microchip Technology Inc.
DS30272A-page 145