PIC16(L)F1512/3
20.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator
available for clock generation in both I2C and SPI
Master modes. The Baud Rate Generator (BRG)
reload value is placed in the SSPADD register
(Register 20-6). When a write occurs to SSPBUF, the
Baud Rate Generator will automatically begin counting
down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in Figure 20-39 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 20-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 20-1:
FCLOCK = ---S---S----P----A----FD---O-D---S--C-+------1--------4----
FIGURE 20-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
SSPCLK
BRG Down Counter
FOSC/2
Note:
Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 20-4: MSSP CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
16 MHz
4 MHz
09h
400 kHz(1)
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
Note 1: Refer to the I/O port electrical specifications in Table 25-4 to ensure the system is designed to support lol
requirements.
DS40001624C-page 222
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