PIC16LF1902-I/P View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LF1902-I/P

28-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology

Microchip Technology 

10.0 FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable

during normal operation over the full VDD range.

Program memory is indirectly addressed using Special

Function Registers (SFRs). The SFRs used to access

program memory are:

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word

that holds the 14-bit data for read/write, and the

PMADRL and PMADRH registers form a 2-byte word

that holds the 15-bit address of the program memory

location being read.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device.

The Flash Program Memory Self-Write Protection bits,

WRT<1:0> of Configuration Word 2, can be used to

prohibit self-writes to a portion or all of the Flash

program memory.

When the device is code-protected (CP = 0)(1), the

device programmer can no longer access program

memory. When code-protected, the CPU may continue

to read and self-write program memory.

Note 1: Code protection of the entire Flash

Program Memory array is enabled by

clearing the CP bit of Configuration Word

1.

PIC16LF1902/3

10.1 PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up

to a maximum of 32K words of program memory. When

selecting a program address value, the MSB of the

address is written to the PMADRH register and the LSB

is written to the PMADRL register.

10.1.1

PMCON1 AND PMCON2

REGISTERS

PMCON1 is the control register for Flash Program

Memory accesses.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared by hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation to

occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted

by a Reset during normal operation. In these situations,

following Reset, the user can check the WRERR bit

and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting

to read the PMCON2 register will return all ‘0’s.

To enable writes to the program memory, a specific

pattern (the unlock sequence), must be written to the

PMCON2 register. The required unlock sequence

prevents inadvertent writes to the program memory

write latches and Flash program memory.

 2011 Microchip Technology Inc.

Preliminary

DS41455A-page 79

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