PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

FIGURE 16-5: ASYNCHRONOUS RECEPTION

RX (pin)

Rcv shift

reg

Rcv buffer reg

Read Rcv

buffer reg

RCREG

START

bit bit0 bit1

START

bit7/8 STOP bit bit0

bit

Word 1

RCREG

RCIF

(interrupt flag)

START

bit7/8 STOP bit

bit

Word 2

RCREG

bit7/8 STOP

bit

OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

TABLE 16-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

PIR1

PIE1

IPR1

RCSTA

RCREG

TXSTA

SPBRG

GIE/GIEH PEIE/GIEL TMR0IE

PSPIF

ADIF

RCIF

PSPIE

ADIE

RCIE

PSPIP

ADIP

RCIP

SPEN

RX9

SREN

INT0IE

TXIF

TXIE

TXIP

CREN

RBIE

SSPIF

SSPIE

SSPIP

—

TMR0IF INT0IF RBIF

CCP1IF TMR2IF TMR1IF

CCP1IE TMR2IE TMR1IE

CCP1IP TMR2IP TMR1IP

FERR OERR RX9D

USART Receive Register

CSRC

TX9

TXEN SYNC ADDEN BRGH TRMT TX9D

Baud Rate Generator Register

0000 000x

0000 0000

0000 0000

0000 0000

0000 -00x

0000 0000

0000 0010

0000 0000

0000 000u

0000 0000

0000 0000

0000 0000

0000 -00x

0000 0000

0000 0010

0000 0000

Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

DS30475A-page 176

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 2000 Microchip Technology Inc.

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