PIC18CXX8
17.2.6 CAN MODULE I/O CONTROL REGISTER
This subsection describes the CAN Module I/O Control
register.
REGISTER 17-32: CIOCON – CAN I/O CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0
U-0
U-0
U-0
U-0
TX1SRC TX1EN ENDRHI CANCAP —
—
—
—
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
TX1SRC: CAN TX1 Pin Data Source
1 = CAN TX1 pin will output the CAN clock
0 = CAN TX1 pin will output TXD
TX1EN: CAN TX1 Pin Enable
1 = CAN TX1 pin will output TXD or CAN clock
0 = CAN TX1 pin will have digital I/O function
ENDRHI: Enable Drive High
1 = CAN TX0, CAN TX1 pins will drive VDD when recessive
0 = CAN TX0, CAN TX1 pins will tri-state when recessive
CANCAP: CAN Message Receive Capture Enable
1 = Enable CAN capture
0 = Disable CAN capture
Unimplemented: Read as ’0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 205