PIC18LC658-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LC658-I/CL

High-Performance Microcontrollers with CAN Module

Microchip Technology 

PIC18CXX8

2.5 HS4 (PLL)

A Phase Locked Loop circuit is provided as a pro-

grammable option for users that want to multiply the

frequency of the incoming crystal oscillator signal by 4.

For an input clock frequency of 10 MHz, the internal

clock frequency will be multiplied to 40 MHz. This is

useful for customers who are concerned with EMI due

to high frequency crystals.

FIGURE 2-5: PLL BLOCK DIAGRAM

The PLL can only be enabled when the oscillator con-

figuration bits are programmed for HS mode. If they

are programmed for any other mode, the PLL is not

enabled and the system clock will come directly from

OSC1.

The PLL is one of the modes of the FOSC2:FOSC0

configuration bits. The oscillator mode is specified dur-

ing device programming.

A PLL lock timer is used to ensure that the PLL has

locked before device execution starts. The PLL lock

timer has a time-out referred to as TPLL.

FOSC2:FOSC0 = ‘110’

OSC2

OSC1

Crystal

Osc

Phase

Comparator

FIN

FOUT

Loop

Filter

VCO

Divide by 4

SYSCLK

DS30475A-page 24

Advanced Information

 2000 Microchip Technology Inc.

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