PIC18LF1320-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF1320-I/SOSQTP

18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Microchip Technology 

PIC18F1220/1320

BNOV

Branch if Not Overflow

Syntax:

[ label ] BNOV n

Operands:

-128 ≤ n ≤ 127

Operation:

if Overflow bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1110 0101 nnnn nnnn

Description:

If the Overflow bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then

a two-cycle instruction.

Words:

1

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

No

operation

If No Jump:

Read literal

‘n’

No

operation

Process

Data

No

operation

Write to PC

No

operation

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

If Overflow =

PC

=

If Overflow =

PC

=

BNOV Jump

address (HERE)

0;

address (Jump)

1;

address (HERE + 2)

BNZ

Branch if Not Zero

Syntax:

[ label ] BNZ n

Operands:

-128 ≤ n ≤ 127

Operation:

if Zero bit is ‘0’

(PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1110 0001 nnnn nnnn

Description:

If the Zero bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then

a two-cycle instruction.

Words:

1

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Q1

Q2

Q3

Q4

Decode

No

operation

If No Jump:

Read literal

‘n’

No

operation

Process

Data

No

operation

Write to PC

No

operation

Q1

Q2

Q3

Q4

Decode

Read literal

‘n’

Process

Data

No

operation

Example:

HERE

Before Instruction

PC

=

After Instruction

If Zero

=

PC

=

If Zero

=

PC

=

BNZ Jump

address (HERE)

0;

address (Jump)

1;

address (HERE + 2)

DS39605F-page 202

© 2007 Microchip Technology Inc.

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