PIC18LF2431-I/ML View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF2431-I/ML

28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D

Microchip Technology 

PIC18F2331/2431/4331/4431

RETURN

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

No

operation

Return from Subroutine

[ label ] RETURN [s]

s  [0,1]

(TOS)  PC;

if s = 1:

(WS)  W,

(STATUSS)  STATUS,

(BSRS)  BSR,

PCLATU, PCLATH are unchanged

None

0000 0000 0001 001s

Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers, WS, STATUSS and BSRS,

are loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs.

1

2

Q2

No

operation

No

operation

Q3

Process

Data

No

operation

Q4

POP PC

from stack

No

operation

Example:

RETURN

After Interrupt

PC = TOS

RLCF

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Rotate Left f through Carry

[ label ] RLCF f [,d [,a]]

0  f  255

d  [0,1]

a  [0,1]

(f<n>)  dest<n + 1>,

(f<7>)  C,

(C)  dest<0>

C, N, Z

0011 01da ffff ffff

The contents of register, ‘f’, are rotated

one bit to the left through the Carry flag.

If ‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in regis-

ter, ‘f’. If ‘a’ is ‘0’, the Access Bank will

be selected, overriding the BSR value.

If ‘a’ = 1, then the bank will be selected

as per the BSR value.

C

register f

Words:

Cycles:

Q Cycle Activity:

Q1

Decode

1

1

Q2

Read

register ‘f’

Q3

Process

Data

Q4

Write to

destination

Example:

RLCF

REG, W

Before Instruction

REG = 1110 0110

C

=0

After Instruction

REG =

W

=

C

=

1110 0110

1100 1100

1

 2010 Microchip Technology Inc.

DS39616D-page 315

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