PIC18F2331/2431/4331/4431
FIGURE 26-6:
OSC1
CLKO
I/O Pin
(Input)
I/O Pin
(Output)
CLKO AND I/O TIMING
Q4
Q1
10
Old Value
13 14
17
20, 21
Q2
19
18
15
Q3
11
12
16
New Value
TABLE 26-7: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
10
TosH2ckL OSC1 to CLKO
—
75
200
ns (Note 1)
11
TosH2ckH OSC1 to CLKO
—
75
200
ns (Note 1)
12
TckR
CLKO Rise Time
—
35
100
ns (Note 1)
13
TckF
CLKO Fall Time
—
35
100
ns (Note 1)
14
TckL2ioV CLKO to Port Out Valid
—
— 0.5 TCY + 20 ns (Note 1)
15
TioV2ckH Port In Valid before CLKO
0.25 TCY + 25 —
—
ns (Note 1)
16
TckH2ioI Port In Hold after CLKO
0
—
—
ns (Note 1)
17
TosH2ioV OSC1 (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TosH2ioI OSC1 (Q2 cycle) to PIC18FXX31
100
—
—
ns
18A
Port Input Invalid
PIC18LFXX31
200
—
—
ns
(I/O in hold time)
19
TioV2osH Port Input Valid to OSC1 (I/O in setup
time)
0
—
—
ns
20
TioR
Port Output Rise Time PIC18FXX31
—
10
25
ns
20A
PIC18LFXX31
—
—
60
ns
21
TioF
Port Output Fall Time PIC18FXX31
—
10
25
ns
21A
PIC18LFXX31
—
—
60
ns
22† TINP
INTx Pin High or Low Time
TCY
—
—
ns
23† TRBP
RB<7:4> Change INTx High or Low Time
TCY
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39616D-page 348
2010 Microchip Technology Inc.