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PIC18LF4550T-I/SO View Datasheet(PDF) - Microchip Technology

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PIC18LF4550T-I/SO Datasheet PDF : 438 Pages
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PIC18F2455/2550/4455/4550
TABLE 28-29: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
0.8 25.0(1) μs TOSC based, VREF 3.0V
1.4 25.0(1) μs VDD = 2.0V,
TOSC based, VREF full range
PIC18FXXXX
1
μs A/D RC mode
PIC18LFXXXX
3
μs VDD = 2.0V,
A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)(2)
132 TACQ Acquisition Time(3)
11
12
TAD
1.4
μs -40°C to +85°C
135 TSWC Switching Time from Convert Sample
(Note 4)
137 TDIS Discharge Time
0.2
μs
Note 1:
2:
3:
4:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
On the following cycle of the device clock.
© 2009 Microchip Technology Inc.
DS39632E-page 405

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