PIC18F44J10T-I/ML(2009) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F44J10T-I/ML
(Rev.:2009)
(Rev.:2009)
Microchip Technology
PIC18F44J10T-I/ML Datasheet PDF : 368 Pages
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PIC18F45J10 FAMILY
TABLE 1-2: PIC18F24J10/25J10 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
SPDIP,
Pin Buffer
SOIC, QFN Type Type
SSOP
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 8
I/O ST
Digital I/O.
O—
Timer1 oscillator output.
I ST
Timer1 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12 9
I/O ST
Digital I/O.
I Analog Timer1 oscillator input.
I/O ST
Capture 2 input/Compare 2 output/PWM2 output.
RC2/CCP1
RC2
CCP1
13 10
I/O ST
I/O ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
14 11
I/O ST
I/O ST
I/O ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
SDI1
SDA1
15 12
I/O ST
I ST
I/O ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
SDO1
16 13
I/O ST
O—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14
I/O ST
O—
I/O ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 15
I/O ST
I ST
I/O ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
VSS
8, 19 5, 16 P —
Ground reference for logic and I/O pins.
VDD
20 17 P —
Positive supply for logic and I/O pins.
VDDCORE/VCAP
VDDCORE
VCAP
6
3
P—
P—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
O = Output
CMOS = CMOS compatible input or output
I
= Input
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2009 Microchip Technology Inc.
DS39682E-page 15
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