PIC18F44J10T-I/ML(2009) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F44J10T-I/ML
(Rev.:2009)
(Rev.:2009)
Microchip Technology
PIC18F44J10T-I/ML Datasheet PDF : 368 Pages
| |||
PIC18F45J10 FAMILY
19.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 19-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 19-4:
COMPARATOR ANALOG INPUT MODEL
VDD
RS < 10k
AIN
VA
CPIN
5 pF
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±100 nA
Comparator
Input
VSS
Legend:
CPIN
=
VT
=
ILEAKAGE =
RIC
=
RS
=
VA
=
Input Capacitance
Threshold Voltage
Leakage Current at the pin due to various junctions
Interconnect Resistance
Source Impedance
Analog Voltage
TABLE 19-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
CMCON
C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0
49
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
49
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
50
PIR2
OSCFIF CMIF
—
—
BCL1IF
—
—
CCP2IF
49
PIE2
OSCFIE CMIE
—
—
BCL1IE
—
—
CCP2IE 49
IPR2
OSCFIP CMIP
—
—
BCL1IP
—
—
CCP2IP 49
PORTA
—
—
RA5
—
RA3
RA2
RA1
RA0
50
LATA
—
—
PORTA Data Latch Register (Read and Write to Data Latch)
50
TRISA
—
—
TRISA5
—
TRISA3 TRISA2 TRISA1 TRISA0
50
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
© 2009 Microchip Technology Inc.
DS39682E-page 229
Share Link: 