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PIC18LF45J10T-I/SP View Datasheet(PDF) - Microchip Technology

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Description
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PIC18LF45J10T-I/SP Datasheet PDF : 358 Pages
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PIC18F45J10 FAMILY
FIGURE 23-5:
OSC1
CLKO AND I/O TIMING
Q4
Q1
10
CLKO
13
14
I/O pin
(Input)
17
I/O pin
(Output)
Old Value
Note:
20, 21
Refer to Figure 23-3 for load conditions.
Q2
Q3
11
19
18
12
16
15
New Value
TABLE 23-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10
TOSH2CKL OSC1 to CLKO
75
200
ns
11
TOSH2CKH OSC1 to CLKO
75
200
ns
12
TCKR
CLKO Rise Time
15
30
ns
13
TCKF
CLKO Fall Time
15
30
ns
14
TCKL2IOV CLKO to Port Out Valid
— 0.5 TCY + 20 ns
15
TIOV2CKH Port In Valid before CLKO
0.25 TCY + 25 —
ns
16
TCKH2IOI Port In Hold after CLKO
0
ns
17
TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid
50
150
ns
18
TOSH2IOI OSC1 (Q2 cycle) to Port Input Invalid
18A
(I/O in hold time)
100
ns
200
ns
19
TIOV2OSH Port Input Valid to OSC1
(I/O in setup time)
0
ns
20
TIOR
Port Output Rise Time
TBD
6
ns
21
TIOF
Port Output Fall Time
TBD
5
ns
22† TINP
INT pin High or Low Time
TCY
ns
23† TRBP
RB7:RB4 Change INT High or Low Time
TCY
ns
Legend: TBD = To Be Determined
† These parameters are asynchronous events not related to any internal clock edges.
© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 313

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