PIC18LF45J10T-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF45J10T-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

TABLE 23-21: MASTER SSP I2C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max Units

Conditions

100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

102 TR

SDAx and SCLx 100 kHz mode

Rise Time

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

1000

300

300

ns CB is specified to be from

ns 10 to 400 pF

ns

103 TF

SDAx and SCLx 100 kHz mode

Fall Time

400 kHz mode

1 MHz mode(1)

—

20 + 0.1 CB

—

300 ns CB is specified to be from

300 ns 10 to 400 pF

100 ns

90

TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms Repeated Start

condition

ms

91

THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period, the first

Hold Time

400 kHz mode 2(TOSC)(BRG + 1) —

ms clock pulse is generated

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

106 THD:DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

0

0

TBD

—

ns

0.9 ms

—

ns

107 TSU:DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode(1)

250

100

TBD

—

ns (Note 2)

—

ns

—

ns

92

TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) — ms

Setup Time

400 kHz mode 2(TOSC)(BRG + 1) — ms

1 MHz mode(1) 2(TOSC)(BRG + 1) —

ms

109 TAA

Output Valid

from Clock

100 kHz mode

400 kHz mode

1 MHz mode(1)

—

3500 ns

—

1000 ns

—

—

ns

110 TBUF Bus Free Time 100 kHz mode

400 kHz mode

1 MHz mode(1)

4.7

1.3

TBD

— ms Time the bus must be free

—

ms before a new transmission

can start

— ms

D102 CB

Bus Capacitive Loading

—

400 pF

Legend:

Note 1:

2:

TBD = To Be Determined

Maximum pin capacitance = 10 pF for all I2C™ pins.

A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data

bit to the SDAx line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before

the SCLx line is released.

DS39682C-page 324

Preliminary

© 2007 Microchip Technology Inc.

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