PIC18LF45J10-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF45J10-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1 R/W-1

R/W-1

R/W-1

U-0

R/W-1

U-0

RBPU INTEDG0 INTEDG1 INTEDG2

—

TMR0IP

—

bit 7

R/W-1

RBIP

bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 Unimplemented: Read as ‘0’

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1 Unimplemented: Read as ‘0’

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 = High priority

0 = Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs regardless of the state

of its corresponding enable bit or the global interrupt enable bit. User software should

ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This

feature allows for software polling.

DS39682C-page 82

Preliminary

© 2007 Microchip Technology Inc.

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