PIC18LF45J10-I/SP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18LF45J10-I/SP

28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology

Microchip Technology 

PIC18F45J10 FAMILY

8.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2, IPR3). Using

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

REGISTER 8-10:

IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1

R/W-1

PSPIP(1)

R/W-1

ADIP

R/W-1

RCIP

R/W-1

TXIP

R/W-1 R/W-1

SSP1IP CCP1IP

bit 7

R/W-1

TMR2IP

R/W-1

TMR1IP

bit 0

bit 7

PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)

1 = High priority

0 = Low priority

Note: This bit is not implemented on 28-pin devices and should be read as ‘0’.

bit 6

ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5

RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4

TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3

SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 2

CCP1IP: ECCP1/CCP1 Interrupt Priority bit

1 = High priority

0 = Low priority

bit 1

TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 = High priority

0 = Low priority

bit 0

TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39682C-page 88

Preliminary

© 2007 Microchip Technology Inc.

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