PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F45J50-I/SOSQTP
Microchip Technology
PIC18F45J50-I/SOSQTP Datasheet PDF : 562 Pages
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PIC18F46J50 FAMILY
4.6.9 DEEP SLEEP MODE REGISTERS
Deep Sleep mode registers are provided in
Register 4-1 through Register 4-6.
REGISTER 4-1:
R/W-0
DSEN(1)
bit 7
DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
r
DSULPEN RTCWDIS
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-3
bit 2
bit 1
bit 0
DSEN: Deep Sleep Enable bit(1)
1 = Deep Sleep mode is entered on a SLEEP command
0 = Sleep mode is entered on a SLEEP command
Unimplemented: Read as ‘0’
Reserved: Always write ‘0’ to this bit
DSULPEN: Ultra Low-Power Wake-up Module Enable bit
1 = ULPWU module is enabled in Deep Sleep
0 = ULPWU module is disabled in Deep Sleep
RTCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled
Note 1: In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN.
REGISTER 4-2:
U-0
—
bit 7
DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch)
U-0
U-0
U-0
U-0
R/W-0
R/W-0(1)
R/W-0(1)
—
—
—
—
ULPWDIS
DSBOR RELEASE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ULPWDIS: Ultra Low-Power Wake-up Disable bit
1 = ULPWU wake-up source is disabled
0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1)
DSBOR: Deep Sleep BOR Event Status bit
1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep,
but did not fall below VDSBOR
0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep
RELEASE: I/O Pin State Release bit
Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will
release the I/O pins and allow their respective TRIS and LAT bits to control their states.
Note 1: This is the value when VDD is initially applied.
2011 Microchip Technology Inc.
DS39931D-page 57
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