PIC18F45J50-I/SOSQTP View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC18F45J50-I/SOSQTP

28/44-Pin, Low-Power, High-Performance USB Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC18F46J50 FAMILY

REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0

(BANKED F4Eh)

R/W-xxxx(1)

Deep Sleep Persistent General Purpose bits

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

Deep Sleep Persistent General Purpose bits

Contents are retained even in Deep Sleep mode.

Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep

Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the

DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.

REGISTER 4-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1

(BANKED F4Fh)

R/W-xxxx(1)

Deep Sleep Persistent General Purpose bits

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-0

Deep Sleep Persistent General Purpose bits

Contents are retained even in Deep Sleep mode.

Note 1: All register bits are maintained unless: VDDCORE drops below the normal BOR threshold outside of Deep

Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the

DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS.

DS39931D-page 58

 2011 Microchip Technology Inc.

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