PIC18F26K22T-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F26K22T-I/ML
Microchip Technology
PIC18F26K22T-I/ML Datasheet PDF : 494 Pages
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PIC18(L)F2X/4XK22
Asynchronous Counter Mode .................................. 165
Reading and Writing ........................................ 165
Clock Source Selection ............................................ 164
Interrupt .................................................................... 168
Operation ................................................................. 164
Operation During Sleep ........................................... 168
Oscillator .................................................................. 165
Prescaler .................................................................. 165
Timer1 Gate
Selecting Source .............................................. 166
TMR1H Register ...................................................... 163
TMR1L Register ....................................................... 163
Timer2
Associated registers ................................................. 178
Timer2/4/6 ........................................................................ 175
Associated registers ................................................. 178
Timers
Timer1
T1CON ............................................................. 172
T1GCON .......................................................... 173
Timer2/4/6
TXCON ............................................................ 177
Timing Diagrams
A/D Conversion ........................................................ 461
Acknowledge Sequence .......................................... 248
Asynchronous Reception ......................................... 273
Asynchronous Transmission .................................... 268
Asynchronous Transmission (Back to Back) ........... 269
Auto Wake-up Bit (WUE) During Normal Operation 283
Auto Wake-up Bit (WUE) During Sleep ................... 283
Automatic Baud Rate Calculator .............................. 282
Baud Rate Generator with Clock Arbitration ............ 241
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 252
Brown-out Reset (BOR) ........................................... 448
Bus Collision During a Repeated Start Condition
(Case 1) ........................................................... 253
Bus Collision During a Repeated Start Condition
(Case 2) ........................................................... 253
Bus Collision During a Start Condition (SCL = 0) .... 252
Bus Collision During a Stop Condition (Case 1) ...... 254
Bus Collision During a Stop Condition (Case 2) ...... 254
Bus Collision During Start Condition (SDA only) ..... 251
Bus Collision for Transmit and Acknowledge ........... 250
Capture/Compare/PWM (CCP) ................................ 450
CLKO and I/O .......................................................... 447
Clock Synchronization ............................................. 238
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 307
EUSART Synchronous Receive (Master/Slave) ...... 460
EUSART Synchronous Transmission
(Master/Slave) .................................................. 460
Example SPI Master Mode (CKE = 0) ..................... 451
Example SPI Master Mode (CKE = 1) ..................... 452
Example SPI Master Mode Timing .......................... 451
Example SPI Slave Mode (CKE = 0) ....................... 453
Example SPI Slave Mode (CKE = 1) ....................... 454
External Clock (All Modes except PLL) .................... 445
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................ 242
Full-Bridge PWM Output .......................................... 195
Half-Bridge PWM Output ................................. 193, 199
High/Low-Voltage Detect Characteristics ................ 442
High-Voltage Detect Operation (VDIRMAG = 1) ...... 348
I2C Bus Data ............................................................ 456
I2C Bus Start/Stop Bits ............................................ 455
I2C Master Mode (7 or 10-Bit Transmission) ........... 245
I2C Master Mode (7-Bit Reception) .......................... 247
I2C Stop Condition Receive or Transmit Mode ........ 249
Internal Oscillator Switch Timing ............................... 43
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 347
Master SSP I2C Bus Data ........................................ 458
Master SSP I2C Bus Start/Stop Bits ........................ 458
PWM Auto-shutdown ............................................... 198
Firmware Restart ............................................. 198
PWM Direction Change ........................................... 196
PWM Direction Change at Near 100% Duty Cycle .. 197
PWM Output (Active-High) ...................................... 191
PWM Output (Active-Low) ....................................... 192
Repeat Start Condition ............................................ 243
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) .......... 448
Send Break Character Sequence ............................ 284
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 65
SPI Mode (Master Mode) ......................................... 215
Synchronous Reception (Master Mode, SREN) ...... 289
Synchronous Transmission ..................................... 286
Synchronous Transmission (Through TXEN) .......... 286
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) .......................................... 66
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 1) ................................... 64
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 2) ................................... 65
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ....................... 64
Timer0 and Timer1 External Clock .......................... 449
Timer1 Incrementing Edge ...................................... 169
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 49
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
Timing Diagrams and Specifications ............................... 445
A/D Conversion Requirements ................................ 462
Capture/Compare/PWM Requirements ................... 451
CLKO and I/O Requirements ................................... 447
EUSART Synchronous Receive Requirements ....... 460
EUSART Synchronous Transmission
Requirements .................................................. 460
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 452
(Master Mode, CKE = 1) .................................. 453
(Slave Mode, CKE = 0) .................................... 454
(Slave Mode, CKE = 1) .................................... 455
External Clock Requirements .................................. 445
I2C Bus Data Requirements (Slave Mode) .............. 457
I2C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 456
Master SSP I2C Bus Data Requirements ................ 459
Master SSP I2C Bus Start/Stop Bits Requirements . 458
PLL Clock ................................................................ 446
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements .................................................. 448
Timer0 and Timer1 External Clock Requirements ... 449
DS41412A-page 488
Preliminary
2010 Microchip Technology Inc.
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