PIC18F8527-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18F8527-I
Microchip Technology
PIC18F8527-I Datasheet PDF : 448 Pages
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PIC18F8722 FAMILY
TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ---- 59, 252
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000 59, 252
RCREG1
EUSART1 Receive Register
0000 0000 59, 260
TXREG1
EUSART1 Transmit Register
0000 0000 59, 257
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 59, 248
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 59, 249
EEADRH
—
—
—
—
—
—
EEPROM Address
---- --00 59, 111
Register High Byte
EEADR
EEPROM Address Register Low Byte
0000 0000 59, 111
EEDATA
EEPROM Data Register
0000 0000 59, 111
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 59, 88
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 59, 89
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
TMR4IP
CCP5IP
CCP4IP
CCP3IP 1111 1111 60, 131
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
CCP3IF 0000 0000 60, 125
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
TMR4IE
CCP5IE
CCP4IE
CCP3IE 0000 0000 60, 128
IPR2
OSCFIP
CMIP
—
EEIP
BCL1IP
HLVDIP
TMR3IP
CCP2IP 11-1 1111 60, 131
PIR2
OSCFIF
CMIF
—
EEIF
BCL1IF
HLVDIF
TMR3IF
CCP2IF 00-0 0000 60, 125
PIE2
OSCFIE
CMIE
—
EEIE
BCL1IE
HLVDIE
TMR3IE
CCP2IE 00-0 0000 60, 128
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP 1111 1111 60, 130
PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF 0000 0000 60, 124
PIE1
MEMCON(2)
OSCTUNE
TRISJ(2)
TRISH(2)
PSPIE
EBDIS
INTSRC
TRISJ7
TRISH7
ADIE
—
PLLEN(3)
TRISJ6
TRISH6
RC1IE
WAIT1
—
TRISJ5
TRISH5
TX1IE
WAIT0
TUN4
TRISJ4
TRISH4
SSP1IE
—
TUN3
TRISJ3
TRISH3
CCP1IE
—
TUN2
TRISJ2
TRISH2
TMR2IE
WM1
TUN1
TRISJ1
TRISH1
TMR1IE
WM0
TUN0
TRISJ0
TRISH0
0000 0000
0-00 --00
00-0 0000
1111 1111
1111 1111
60, 127
60, 96
35, 60
60, 157
60, 155
TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
TRISG0 ---1 1111 60, 153
TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0 1111 1111 60, 150
TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0 1111 1111 60, 148
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 60, 143
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0 1111 1111 60, 140
TRISB
TRISA
LATJ(2)
LATH(2)
LATG
TRISB7
TRISA7(4)
LATJ7
LATH7
—
TRISB6
TRISA6(4)
LATJ6
LATH6
—
TRISB5
TRISA5
LATJ5
LATH5
LATG5(5)
TRISB4
TRISA4
LATJ4
LATH4
LATG4
TRISB3
TRISA3
LATJ3
LATH3
LATG3
TRISB2
TRISA2
LATJ2
LATH2
LATG2
TRISB1
TRISA1
LATJ1
LATH1
LATG1
TRISB0
TRISA0
LATJ0
LATH0
LATG0
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
--xx xxxx
60, 137
60, 135
60, 156
60, 154
60, 151
LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0 xxxx xxxx 60, 149
LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0 xxxx xxxx 60, 146
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 60, 143
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 xxxx xxxx 60, 140
LATB
LATA
LATB7
LATA7(4)
LATB6
LATA6(4)
LATB5
LATA5
LATB4
LATA4
LATB3
LATA3
LATB2
LATA2
LATB1
LATA1
LATB0
LATA0
xxxx xxxx 60, 137
xxxx xxxx 60, 135
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise, this bit reads as ‘0’.
These registers and/or bits are not implemented on 64-pin devices and are read as ‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 and LATG5 read as ‘0’.
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device configuration bits.
DS39646B-page 78
Preliminary
2004 Microchip Technology Inc.
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