PIC18F6310/6410/8310/8410
FIGURE 1-1:
PIC18F6310/6410 (64-PIN) BLOCK DIAGRAM
Table Pointer<21>
inc/dec logic
21
20
Address Latch
Program Memory
(48/64 Kbytes)
Data Latch
Data Bus<8>
88
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
STKPTR
Data Latch
Data Memory
(8/16 Kbytes)
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Access
Bank
12
8
Table Latch
inc/dec
logic
ROM Latch
Instruction Bus <16>
IR
Address
Decode
OSC1(3)
OSC2(3)
T1OSI
T1OSO
MCLR(2)
VDD, VSS
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
3
BITOP
8
8 x 8 Multiply
8
W
8
8
8
8
ALU<8>
8
Precision
Band Gap
Reference
BOR
HLVD
ADC
10-bit
Timer0
Timer1
Timer2
Timer3
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
Comparators CCP1
CCP2
CCP3
MSSP EUSART1 AUSART2
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/HLVDIN
OSC2/CLKO(3)/RA6
OSC1/CLKI(3)/RA7
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
RD7/PSP7:RD0/PSP0
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
RE6
RE7/CCP2(1)
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3
RG4
RG5(2)/MCLR/VPP
Note 1:
2:
3:
CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RE7 when CCP2MX is not set.
RG5 is only available when MCLR functionality is disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39635A-page 10
Preliminary
2004 Microchip Technology Inc.