PIC18F6310/6410/8310/8410
26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
1
2
3
4
Note 1:
FOSC
External CLKI Frequency(1)
DC
Oscillator Frequency(1)
DC
40
MHz EC, ECIO
4
MHz RC oscillator
0.1
4
MHz XT oscillator
4
25
MHz HS oscillator
4
10
MHz HS + PLL oscillator
5
200
kHz LP Oscillator mode
TOSC
External CLKI Period(1)
25
—
ns EC, ECIO
Oscillator Period(1)
250
—
ns RC oscillator
250
10,000 ns XT oscillator
25
250
ns HS oscillator
100
250
ns HS + PLL oscillator
25
—
µs LP oscillator
TCY
Instruction Cycle Time(1)
100
—
ns TCY = 4/FOSC
TOSL, External Clock in (OSC1)
30
TOSH
High or Low Time
2.5
—
ns XT oscillator
—
µs LP oscillator
10
—
ns HS oscillator
TOSR, External Clock in (OSC1)
—
TOSF
Rise or Fall Time
—
20
ns XT oscillator
50
ns LP oscillator
—
7.5
ns HS oscillator
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39635A-page 360
Preliminary
2004 Microchip Technology Inc.