PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF8410-I/PTQTP Datasheet PDF : 404 Pages
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PIC18F6310/6410/8310/8410
INDEX
A
A/D ................................................................................... 245
A/D Converter Interrupt, Configuring ....................... 249
Acquisition Requirements ........................................ 250
ADCON0 Register .................................................... 245
ADCON1 Register .................................................... 245
ADCON2 Register .................................................... 245
ADRESH Register ............................................ 245, 248
ADRESL Register .................................................... 245
Analog Port Pins ...................................................... 140
Analog Port Pins, Configuring .................................. 252
Associated Registers ............................................... 254
Automatic Acquisition Time ...................................... 251
Calculating the Minimum Required
Acquisition Time .............................................. 250
Configuring the Module ............................................ 249
Conversion Clock (TAD) ........................................... 251
Conversion Status (GO/DONE Bit) .......................... 248
Conversions ............................................................. 253
Converter Characteristics ........................................ 377
Discharge ................................................................. 253
Operation in Power Managed Modes ...................... 252
Special Event Trigger (CCP) .................................... 254
Use of the CCP2 Trigger .......................................... 254
Absolute Maximum Ratings ............................................. 343
AC (Timing) Characteristics ............................................. 358
Load Conditions for Device
Timing Specifications ....................................... 359
Parameter Symbology ............................................. 358
Temperature and Voltage Specifications ................. 359
Timing Conditions .................................................... 359
Access Bank ...................................................................... 71
ACKSTAT ........................................................................ 199
ACKSTAT Status Flag ..................................................... 199
ADCON0 Register ............................................................ 245
GO/DONE Bit ........................................................... 248
ADCON1 Register ............................................................ 245
ADCON2 Register ............................................................ 245
ADDFSR .......................................................................... 330
ADDLW ............................................................................ 293
Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART).
See AUSART.
ADDULNK ........................................................................ 330
ADDWF ............................................................................ 293
ADDWFC ......................................................................... 294
ADRESH Register ............................................................ 245
ADRESL Register .................................................... 245, 248
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................ 294
ANDWF ............................................................................ 295
Assembler
MPASM Assembler .................................................. 337
AUSART
Asynchronous Mode ................................................ 236
Associated Registers, Receive ........................ 239
Associated Registers, Transmit ....................... 237
Receiver ........................................................... 238
Setting up 9-bit Mode with Address Detect ...... 238
Transmitter ....................................................... 236
Baud Rate Generator (BRG) ................................... 234
Associated Registers ....................................... 234
Baud Rate Error, Calculating ........................... 234
Baud Rates, Asynchronous Modes ................. 235
High Baud Rate Select (BRGH Bit) ................. 234
Operation in Power Managed Modes .............. 234
Sampling ......................................................... 234
Synchronous Master Mode ...................................... 240
Associated Registers, Receive ........................ 242
Associated Registers, Transmit ....................... 241
Reception ........................................................ 242
Transmission ................................................... 240
Synchronous Slave Mode ........................................ 243
Associated Registers, Receive ........................ 244
Associated Registers, Transmit ....................... 243
Reception ........................................................ 244
Transmission ................................................... 243
Auto-Wake-up on Sync Break Character ......................... 222
B
Bank Select Register (BSR) .............................................. 69
Baud Rate Generator ...................................................... 195
BC .................................................................................... 295
BCF ................................................................................. 296
BF .................................................................................... 199
BF Status Flag ................................................................. 199
Block Diagrams
16-Bit Byte Select Mode ............................................ 93
16-Bit Byte Write Mode .............................................. 91
16-Bit Word Write Mode ............................................ 92
8-Bit Multiplexed Mode .............................................. 96
A/D ........................................................................... 248
Analog Input Model .................................................. 249
AUSART Receive .................................................... 238
AUSART Transmit ................................................... 236
Baud Rate Generator .............................................. 195
Capture Mode Operation ......................................... 161
Comparator
I/O Operating Modes ....................................... 256
Comparator Analog Input Model .............................. 259
Comparator Output .................................................. 258
Comparator Voltage Reference ............................... 262
Compare Mode Operation ....................................... 163
Device Clock .............................................................. 34
EUSART Receive .................................................... 220
EUSART Transmit ................................................... 218
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 51
Fail-Safe Clock Monitor ........................................... 282
Generic I/O Port Operation ...................................... 117
High/Low-Voltage Detect with
External Input .................................................. 266
Interrupt Logic .......................................................... 102
MSSP (I2C Master Mode) ........................................ 193
MSSP (I2C Mode) .................................................... 178
MSSP (SPI Mode) ................................................... 169
On-Chip Reset Circuit ................................................ 49
PIC18F6310/6410 ..................................................... 10
PIC18F8310/8410 ..................................................... 11
PLL (HS Mode) .......................................................... 31
PORTD and PORTE (Parallel Slave Port) ............... 140
PWM Operation (Simplified) .................................... 165
2004 Microchip Technology Inc.
Preliminary
DS39635A-page 389
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