PIC18LF8410-I/PTQTP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF8410-I/PTQTP Datasheet PDF : 404 Pages
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PIC18F6310/6410/8310/8410
PUSH and POP Instructions .............................................. 65
PUSHL ............................................................................. 332
PWM (CCP Module)
Associated Registers ............................................... 167
Duty Cycle ................................................................ 166
Example Frequencies/Resolutions .......................... 166
Period ....................................................................... 165
Setup for PWM Operation ........................................ 166
TMR2 to PR2 Match ................................................ 165
Q
Q Clock ............................................................................ 166
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 31
RCIO Oscillator Mode ................................................ 31
RCALL .............................................................................. 317
RCON Register
Bit Status During Initialization .................................... 56
Register File ....................................................................... 71
Register File Summary ................................................. 73–76
Registers
ADCON0 (A/D Control 0) ......................................... 245
ADCON1 (A/D Control 1) ......................................... 246
ADCON2 (A/D Control 2) ......................................... 247
BAUDCON1 (Baud Rate Control 1) ......................... 212
CCPxCON (Capture/Compare/PWM Control –
CCP1, CCP2, CCP3) ....................................... 159
CMCON (Comparator Control) ................................ 255
CONFIG1H (Configuration 1 High) .......................... 272
CONFIG2H (Configuration 2 High) .......................... 274
CONFIG2L (Configuration 2 Low) ............................ 273
CONFIG3H (Configuration 3 High) .......................... 275
CONFIG3L (Configuration 3 Low) ............................ 275
CONFIG3L (Configuration Byte 3 Low) ..................... 62
CONFIG4L (Configuration 4 Low) ............................ 276
CONFIG5L (Configuration 5 Low) ............................ 276
CONFIG7L (Configuration 7 Low) ............................ 277
CVRCON (Comparator Voltage
Reference Control) ........................................... 261
Device ID Register 1 ................................................ 278
Device ID Register 2 ................................................ 278
HLVDCON (HLVD Control) ...................................... 265
INTCON (Interrupt Control) ...................................... 103
INTCON2 (Interrupt Control 2) ................................. 104
INTCON3 (Interrupt Control 3) ................................. 105
IPR1 (Peripheral Interrupt Priority 1) ........................ 112
IPR2 (Peripheral Interrupt Priority 2) ........................ 113
IPR3 (Peripheral Interrupt Priority 3) ........................ 114
MEMCON (Memory Control) ...................................... 89
OSCCON (Oscillator Control) .................................... 36
OSCTUNE (Oscillator Tuning) ................................... 33
PIE1 (Peripheral Interrupt Enable 1) ........................ 109
PIE2 (Peripheral Interrupt Enable 2) ........................ 110
PIE3 (Peripheral Interrupt Enable 3) ........................ 111
PIR1 (Peripheral Interrupt Request
(Flag) 1) ........................................................... 106
PIR2 (Peripheral Interrupt Request
(Flag) 2) ........................................................... 107
PIR3 (Peripheral Interrupt Request
(Flag) 3) ........................................................... 108
PSPCON (Parallel Slave Port Control) .................... 141
RCON (Reset Control) ....................................... 50, 115
RCSTA1 (EUSART Receive Status
and Control) ..................................................... 211
RCSTA2 (AUSART Receive Status
and Control) ..................................................... 233
SSPCON1 (MSSP Control 1, I2C Mode) ................. 180
SSPCON1 (MSSP Control 1, SPI Mode) ................. 171
SSPCON2 (MSSP Control 2, I2C Mode) ................. 181
SSPSTAT (MSSP Status, I2C Mode) ...................... 179
SSPSTAT (MSSP Status, SPI Mode) ...................... 170
Status ........................................................................ 77
STKPTR (Stack Pointer) ............................................ 65
T0CON (Timer0 Control) ......................................... 143
T1CON (Timer1 Control) ......................................... 147
T2CON (Timer 2 Control) ........................................ 153
T3CON (Timer3 Control) ......................................... 155
TXSTA1 (EUSART Transmit Status
and Control) ..................................................... 210
TXSTA2 (AUSART Transmit Status
and Control) ..................................................... 232
WDTCON (Watchdog Timer Control) ...................... 280
Reset ................................................................................. 49
MCLR Reset, Normal Operation ................................ 49
MCLR Reset, Power Managed Modes ...................... 49
Power-on Reset (POR) .............................................. 49
Programmable Brown-out Reset (BOR) .................... 49
RESET Instruction ..................................................... 49
Stack Full Reset ......................................................... 49
Stack Underflow Reset .............................................. 49
Watchdog Timer (WDT) Reset .................................. 49
Resets .............................................................................. 271
RETFIE ............................................................................ 318
RETLW ............................................................................ 318
RETURN .......................................................................... 319
Return Address Stack ........................................................ 64
Return Stack Pointer (STKPTR) ........................................ 65
Revision History ............................................................... 385
RLCF ............................................................................... 319
RLNCF ............................................................................. 320
RRCF ............................................................................... 320
RRNCF ............................................................................ 321
Run Modes
PRI_RUN ................................................................... 40
RC_RUN .................................................................... 42
SEC_RUN .................................................................. 40
S
SCK ................................................................................. 169
SDI ................................................................................... 169
SDO ................................................................................. 169
Serial Clock, SCK ............................................................ 169
Serial Data In (SDI) .......................................................... 169
Serial Data Out (SDO) ..................................................... 169
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 321
Slave Select (SS) ............................................................. 169
SLEEP ............................................................................. 322
Sleep Mode
OSC1 and OSC2 Pin States ...................................... 37
Software Simulator (MPLAB SIM) ................................... 338
Software Simulator (MPLAB SIM30) ............................... 338
Special Event Trigger. See Compare (CCP Module).
Special Features of the CPU ........................................... 271
Special Function Registers ................................................ 72
Map ............................................................................ 72
SPI Mode (MSSP)
Associated Registers ............................................... 177
Bus Mode Compatibility ........................................... 177
Effects of a Reset .................................................... 177
DS39635A-page 396
Preliminary
2004 Microchip Technology Inc.
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