ZPSD211RM View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD211RM Datasheet PDF : 51 Pages
| |||
8.0
Operating Mode
PSD211R Family
The PSD211R operates in 8-bit address/data mode, enabling it to interface directly to a
variety of 8-bit multiplexed microcontrollers. It works as follows: the address/data bus
(AD0-AD7) is bi-directional and permits the latching of the address when the ALE/AS signal
is active. On the same pins, the data is read from or written to the device, depending on the
state of the control signals (WR, RD, etc.). You should connect your MCU according to the
following figure. Ports A through C can be configured according to Table 3, below.
Figure 3. Connecting a PSD211R to an 8-Bit Multiplexed-Bus MCU
Your
8-bit
MCU
AD0 -AD7
A8 -A15
ALE/AS
PSEN
R/ W or WR
RD/E
A19 / CSI
RESET
A16-A181
PA
PSD211R PB
PC
I /O or A0-A7
I /O or CS0-CS7
CS8 -CS10
OR
NOTE: 1. Connect A16-A18 to Port C if your MCU outputs more than 16 bits of address.
Table 3. Bus and Port Configuration Options
Port
A
B
C
Configurations
I/O or low-order (latched) address lines
I/O and/or CS0–CS7
A16-A18 or CS8-CS10
9.0
Programmable
Address
Decoder (PAD)
The PSD211R contains two programmable arrays, referred to as PAD A and PAD B
(Figure 4). PAD A is used to generate chip select signals derived from the input address to
the internal EPROM blocks and I/O ports.
PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the
decoding to select external devices or as a random logic replacement.
PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft based
on the designer’s input. The PAD’s non-volatile configuration is stored in a re-programmable
CMOS EPROM. Windowed packages are available for erasure by the user. See Table 4 for
a list of PAD A and PAD B functions.
9
Share Link: 